Processor system, instruction sequence optimization device,...

Details Processor system, instruction sequence optimization device,... Processor system, instruction sequence optimization device,...

2007-03-12

2009-08-04

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S300000, C713S320000, C713S500000, C713S501000, C718S100000, C718S102000, C718S104000

Reexamination Certificate

active

07571342

ABSTRACT:
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assignment controlling section outputs the instruction code to a CPU or an HWE based on the detection to have the instruction code executed. A clock controlling section supplies a clock signal having a frequency lower than the maximum clock frequency to one of the CPU and the HWE in which a waiting time arises when the CPU and the HWE operate at the maximum clock frequencies, thus reducing power consumption.

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Japanese Office Action issued in corresponding Japanese Patent Application No. JP 2002-363609 dated Sep. 25, 2007.

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