Processor system, instruction sequence optimization device,...

Details Processor system, instruction sequence optimization device,... Processor system, instruction sequence optimization device,...

2007-04-17

2007-04-17

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000, C718S102000

Reexamination Certificate

active

10868357

ABSTRACT:
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assignment controlling section outputs the instruction code to a CPU or an HWE based on the detection to have the instruction code executed. A clock controlling section supplies a clock signal having a frequency lower than the maximum clock frequency to one of the CPU and the HWE in which a waiting time arises when the CPU and the HWE operate at the maximum clock frequencies, thus reducing power consumption.

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Nutt, Gary J., Operating Systems: A Modern Perspective, Addison-Wesley, Second Ed., pp. 155-179.

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