Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2003-09-12
2009-11-03
Nguyen, Van H (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S001000, C718S100000, C718S102000, C712S034000
Reexamination Certificate
active
07614056
ABSTRACT:
An abstraction layer is comprised in the operating system that represents the particulars of the PPMs. The abstractions in the abstraction layer are differentiated from one another by parameters representing the characteristics of the PPMs. The dispatcher uses the abstraction to balance processing loads when assigning execution threads to the PPMs. The assigning of the execution threads and the balancing of the processing loads is performed while taking account of the characteristics of the PPMs, such as shared resources and clock speed.
REFERENCES:
patent: 5937187 (1999-08-01), Kosche et al.
patent: 5960461 (1999-09-01), Frank et al.
patent: 6002870 (1999-12-01), Faulkner et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6105053 (2000-08-01), Kimmel et al.
patent: 6272520 (2001-08-01), Sharangpani et al.
patent: 6298411 (2001-10-01), Giacalone
patent: 6314511 (2001-11-01), Levy et al.
patent: 6330649 (2001-12-01), Frank et al.
patent: 6341347 (2002-01-01), Joy et al.
patent: 6351808 (2002-02-01), Joy et al.
patent: 6493741 (2002-12-01), Emer et al.
patent: 6507862 (2003-01-01), Joy et al.
patent: 6542991 (2003-04-01), Joy et al.
patent: 6598122 (2003-07-01), Mukherjee et al.
patent: 6622217 (2003-09-01), Gharachorloo et al.
patent: 6651158 (2003-11-01), Burns et al.
patent: 6658447 (2003-12-01), Cota-Robles
patent: 7051329 (2006-05-01), Boggs et al.
patent: 7080379 (2006-07-01), Brenner et al.
patent: 2002/0078122 (2002-06-01), Joy et al.
patent: 2002/0138717 (2002-09-01), Joy et al.
patent: 2003/0014612 (2003-01-01), Joy et al.
patent: 2003/0023794 (2003-01-01), Venkitakrishnan et al.
patent: 2003/0046495 (2003-03-01), Venkitakrishnan et al.
patent: 2003/0084269 (2003-05-01), Drysdale et al.
patent: 2003/0126365 (2003-07-01), Jamil et al.
patent: 2003/0191927 (2003-10-01), Joy et al.
patent: 2004/0024874 (2004-02-01), Smith
patent: 2004/0199919 (2004-10-01), Tovinkere
patent: 2004/0215987 (2004-10-01), Farkas et al.
patent: 2004/0268347 (2004-12-01), Knauerhase et al.
patent: 2005/0033831 (2005-02-01), Rashid
patent: 2004171167 (2004-06-01), None
Intel Corporation, “Hyper-Threading Technology on the Intel Xeon Processor Family for Servers,” 2002, pp. 1-12.
Joel M. Tendler et al., “IBM Server POWER4 System Microarchitecture,” Technical White Paper, Oct. 2001, pp. 1-33.
Sandeep Khanna, et al., “Realtime Scheduling in SunOS 5.0,” undated, 16 pages.
J. R. Eykholt, et al., “Beyond Multiprocessing . . . Multithreading the SunOS Kernel,” Summer '92 USENIX—Jun. 8-Jun. 12, 1992, San Antonio, TX, pp. 1-10.
R. C. Agarwal, et al., “Fast Pseudorandom-Number Generators with Modulus 2kor 2k-1 Using Fused Multiply-Add,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 97-116.
G. P. Rodgers, et al., “Infrastructure Requirements for a Large-Scale, Multi-Site VLSI Development Project,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 87-95.
D. C. Bossen, et al., “Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 77-86.
J. M. Ludden, et al., “Functional Verification of the POWER4 Microprocessor and POWER4 Multiprocessor Systems,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 53-76.
J. D. Warnock, et al., “The Circuit and Physical Design of the POWER4 Microprocessor,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 27-51.
J. M. Tendler, et al., “POWER4 System Microarchitecture,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 5-25.
Vijay T. Lund, “Preface,” IBM J. Res. & Dev., vol. 46, No. 1, Jan. 2002, pp. 3-4.
Chew Jonathan
Dorofeev Andrei
Saxe Eric C.
Smaalders Bart
Tucker Andrew G.
Nguyen Van H
Osha • Liang LLP
Sun Microsystems Inc.
Tang Kenneth
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