Processor purging system and method

Details Processor purging system and method Processor purging system and method

2003-08-01

2009-06-02

An, Meng-Ai (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

C711S205000, C711S207000

Reexamination Certificate

active

07543291

ABSTRACT:
A processor purging system comprising a translation lookaside buffer (TLB) having a plurality of translation pairs, at least one memory cache, and logic configured to detect whether at least one of the translation pairs corresponds to a purge signal. The logic is further configured to assert a purge detection signal indicative of whether at least one translation pair corresponds to the purge signal and to determine, based upon the purge detection signal, whether to search the memory cache for a translation pair corresponding to the purge signal.

REFERENCES:
patent: 4733348 (1988-03-01), Hirsoka et al.
patent: 5437017 (1995-07-01), Moore et al.
patent: 5758178 (1998-05-01), Lesartre
patent: 5781918 (1998-07-01), Lieberman et al.
patent: 6539466 (2003-03-01), Riedlinger
patent: 6560689 (2003-05-01), Mathews et al.

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