Processor prefetch to match memory bus protocol characteristics

Details Processor prefetch to match memory bus protocol characteristics Processor prefetch to match memory bus protocol characteristics

2007-01-09

2007-01-09

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S213000, C712S207000

Reexamination Certificate

active

10226158

ABSTRACT:
Memory pages within a memory subsystem are typically accessed using an off chip memory controller coupled to an external bus. Data elements, in the form of a cache line, propagate along the external bus to the processor. Cache line pre-fetching provides a cache line from the memory subsystem to fulfill the processor request. Unfortunately, when the memory subsystem is being accessed by a fetch operation, a subsequent fetch request cannot access the memory subsystem until the previous transaction has completed. Thus subsequent transactions must wait until the previous transaction is completed. This waiting typically results in processor stall cycles, where the processor is stalled in waiting for the memory subsystem to become available. This is especially evident in multi-processor systems, where the addition of another processor does not cause the processing bandwidth to increase substantially. Especially when the processors are waiting for each other's memory subsystem transactions to complete. It would be more advantageous to provide a fetch operation that has a variable fetch size that would allow each of the processor to incur less stall cycles, thus increasing processing bandwidth.

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