Processor multi-partition security architecture

Details Processor multi-partition security architecture Processor multi-partition security architecture

2005-11-10

2009-11-24

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Using table

C711S103000

Reexamination Certificate

active

07624249

ABSTRACT:
A state machine may be coupled to a memory management unit configuration table (MMUCT) stored in a memory to index an entry from the MMUCT. A parameter associated with the entry may be used to control operations associated with a memory management unit (MMU). The MMU may be used to control access to a set of page tables stored in the memory. Other embodiments may be described and claimed.

REFERENCES:
patent: 7149901 (2006-12-01), Herbert et al.
patent: 2006/0271919 (2006-11-01), Moyer
“TrustZone Cores—Secure Processor Core Technology” [on-line], Arm Holdings Ltd. plc, [archived on Dec. 13, 2005]. Retrieved from the Internet: <URL: http://web.archive.org/web/20051213013306/http://www.arm.com/products/esd/trustzone—cores.html>, (2005),1 pg.
“TrustZone System Design—System Hardware Security Control” [on-line], Arm Holdings Ltd. plc, [archived on Dec. 13, 2005]. Retrieved from the Internet: <URL: http://web.archive.org/web/20051213012545/http://www.arm.com/products/esd/trustzone—systemdesign.html, (2005), 3 pgs.
“TrustZone® Security Foundation by ARM®” [on-line], Arm Holdings Ltd. plc, [archived on Dec. 11, 2005]. Retrieved from the Internet: <URL: http://web.archive.org/ web/20051211064714/http://www.arm.com/products/esd/trustzone—home.html>, (2005), 2 pgs.

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