Processor isolation technique for integrated multi-processor...

Details Processor isolation technique for integrated multi-processor... Processor isolation technique for integrated multi-processor...

2007-02-27

2007-02-27

Beausoliel, Jr., Robert W (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S011000

Reexamination Certificate

active

10731971

ABSTRACT:
A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

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