Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-04-21
1998-07-07
Decady, Albert
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711202, 395652, G06F 1100, G06F 1200
Patent
active
057781710
ABSTRACT:
A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip. The maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected, and read out the state of the microprocessors and a secondary cache attached to the microprocessors, before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault.
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Fu Peter
Grosz Martin Jiri
Rahman Mizanur Mohammed
Rector Russell Mark
Sabernick Fred C.
Albert Philip H.
De'cady Albert
Tandem Computers Incorporated
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