Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-02-10
2008-12-16
Duncan, Marc (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C712S227000
Reexamination Certificate
active
07467325
ABSTRACT:
Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
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Eisen Susan Elizabeth
Le Hung Qui
Mack Michael James
Nguyen Dung Quoc
Paredes Jose Angel
Duncan Marc
Glanzman Gerald H.
International Business Machines - Corporation
Lottich Joshua P
Roberts-Gerhardt Diana L.
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