Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-06-15
2003-12-30
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S208000
Reexamination Certificate
active
06671791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to paging systems and, more particularly, to a paging system for translating virtual addresses having more than 32 bits.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Since such processors may execute software from the large body of software written for the x86 architecture, computer systems employing these processors may enjoy increased acceptance in the market due to the large amount of available software.
As computer systems have continued to evolve, 64-bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64-bit address and/or operand sizes. Thus, it may be desirable to provide an architecture which is compatible with the x86 processor architecture but which includes support for 64-bit processing as well.
Unfortunately, extending the x86 processor architecture to 64 bits may be problematic. For example, extending virtual addresses to 64 bits may present challenges. Virtual addresses allow a processor to map pages of virtual memory space to pages in actual physical memory space and/or disk storage space. Before the actual physical memory space can be accessed, the virtual addresses need to be translated to physical addresses. This process is known as address translation or memory mapping, and may be performed by hardware, software, or a combination of both. Typically, virtual addresses are translated to physical addresses using some sort of paging system. These paging systems may be constructed in a way that depends upon the expected virtual and/or physical address sizes. Thus, if virtual addresses are to be extended to 64 bits, the paging system may need to be redefined, creating additional compatibility issues.
Currently, several paging systems are available for the x86 architecture. One such paging system is shown in FIG.
1
. In this paging system, a 32-bit virtual address
101
is being translated to a physical address
121
. Several paging tables
110
, which are used to translate the virtual address, and a 4 kilobyte (Kb) page of physical memory
120
are also shown. Each of the paging tables may be contained in a 4 Kb page that can contain up to 1024 (2
10
) 32-bit entries. In this system, the page directory base register, CR
3
, points to the base address of first paging table, the page directory table
110
a
. The page directory table entries each contain a pointer, and each pointer is a base address of a page table such as page table
110
b
. The upper 10 bits
31
:
22
of the virtual address
101
specify an offset within the page directory
110
a
. Thus, bits
31
:
22
and the pointer in CR
3
can be used to locate entry
111
a
in the page directory table
110
a.
In the illustrated example, the page directory entry
111
a
contains a pointer to the base address of page table
110
b
. The middle field of the virtual address
101
, bits
21
:
12
, specifies an offset within page table
110
b
. This offset and the pointer in page directory entry
111
a
can be used to locate page table entry
111
b
. The page table entry
111
b
contains a pointer, which is a base address of a page of physical memory
120
. The offset specified in the lowest 12 bits
11
:
0
of the virtual address
101
is an offset within the page of physical memory. Thus, the base address found in the page table entry
111
b
can be concatenated with the offset specified in bits
11
:
0
of the virtual address to get the physical address
121
.
One variation of the paging system shown in
FIG. 1
may simply use one paging table. CR
3
may point to a base address of a page directory table, and the upper bits
31
:
22
of the virtual address may specify an offset within that page directory table. The entry in the page directory table located using that offset may contain the base address of a page of physical memory. The lower bits
21
:
0
of the virtual address may then specify the offset within that page to specify the physical address. Because 22 bits are used to specify the offset, the pages of physical memory can be 4 Megabytes (Mb) in size.
In
FIG. 2A
, three paging tables
110
a
-
110
c
(collectively, paging tables
110
) are used for memory mapping. The page directory base register
34
, CR
3
, points to a base address of a page directory pointer table
210
c
. The highest order pair of bits
31
:
30
provides an offset within page directory pointer table
210
c
. Since two bits are used for the offset within the page directory pointer table
210
c
, as opposed to the nine bits used for the other paging tables
210
a
and
210
b
, the first paging table is smaller than the other two paging tables. Thus, page directory pointer table
210
c
may contain a maximum of four entries, while the other two paging tables
210
a
and
210
b
may contain up to 512 (2
9
) entries.
In
FIG. 2A
, three paging tables
110
are used for memory mapping. The page directory base register
34
, CR
3
, points to a base address of a page directory pointer table
210
c
. The highest order pair of bits
31
:
30
provides an offset within page directory pointer table
210
c
. Since two bits are used for the offset within the page directory pointer table
210
, as opposed to the nine bits used for the other paging tables
210
a
and
210
b
, the first paging table is smaller than the other two paging tables. Thus, page directory pointer table
210
c
may contain a maximum of four entries, while the other two paging tables
210
a
and
210
b
may contain up to 512 (2
9
) entries.
The paging tables
210
a
-
210
c
(collectively, paging tables
210
) in
FIG. 2A
may be used to translate a virtual address
201
to a physical address in a manner similar to that described with respect to FIG.
1
. For example, the page directory pointer table entry
211
c
contains the base address of a page directory table
210
a
. Likewise, the directory bits
29
:
21
in the virtual address
201
identify an offset within the page directory table
210
a
, and the entry
211
a
located using that offset contains a pointer to a page table
210
b
. The pointer to the page table and the table bits
20
:
12
in the virtual address
201
, which describe an offset within the page table
210
b
, can be used to locate a page table entry
211
b
. This page table entry
211
b
contains a base address of a page
220
in physical memory, and this base address can be concatenated with the offset bits
11
:
0
in the virtual address
201
to generate the physical address
221
.
FIG. 2B
shows a similar x86 paging system for 36-bit physical addresses. Unlike the system shown in
FIG. 2A
, this system maps virtual addresses to 2 Mb pages and uses two paging tables. Because the physical pages are 2 Mb in size, as opposed to 4 Kb, more bits of the virtual address may be used to specify the offset. Thus, in this embodiment, the lowermost 21 bits of the virtual address specify an offset within a physical page of memory, allowing each page to be 2
21
=2 Mb in size. Generally, the paging tables shown in
FIG. 2B
may be used in much the same manner as those shown in FIG.
2
A.
All of the above paging systems are limited to 32-bit virtual addresses. If more than 32 bits are used, the above systems will not be able to provide unique mapping of virtual addresses to physical address. Therefore, these address translation systems would be unworkable with larger virtual addresses.
SUMMARY
Various embodiments of methods and systems for mapping virtual addresses having more than
Advanced Micro Devices , Inc.
Gossage Glenn
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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