Processor-implemented method of controlling data access to share

Details Processor-implemented method of controlling data access to share Processor-implemented method of controlling data access to share

1997-06-24

1999-05-04

Lim, Krisna

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711130, 395726, 39520043, G06F 946, G06F 1200

Patent

active

059000180

ABSTRACT:
An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of processors to a write-cache to cause the write-cache to obtain exclusive access to a control memory of a shared resource. A first signal is then transmitted to the front end of the processor indicating that the write-cache has obtained exclusive access to the control memory of the shared source. At least one next instruction is executed, and a second signal is transmitted from the front end to the write cache indicating that execution of the at least one next instruction has been completed. Data from the write cache is stored in the control memory of the shared resource in response to the second signal transmitted to the write cache.

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