Processor having interface with bus arbitration circuit

Details Processor having interface with bus arbitration circuit Processor having interface with bus arbitration circuit

1999-04-20

2001-09-18

Pan, Daniel H. (Department: 2183)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S120000, C710S063000, C710S105000, C711S211000

Reexamination Certificate

active

06292861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor having an interface with a bus arbitration circuit and a data processing apparatus using the same.
2. Description of the Related Art
FIG. 8
shows a prior art data processing apparatus consisting of a microprocessor
10
, a buss master
20
, for example, a DMA controller, a memory
21
and an external bus
22
connected therebetween.
FIG. 9
is a timing chart showing arbitrating signals of a bus ownership between the microprocessor
10
and the bus master
20
. An asterisk ‘*’ attached to reference character for signal means that the signal is active when it is low.
The bus master
20
makes the bus request signal *BREQ low when it is going to use the external bus
22
. In response thereto, the microprocessor
10
relinquishes the external bus
22
by setting the output of the microprocessor
10
, to which the external bus
22
is connected, to a high impedance state after the microprocessor
10
completes execution of its present instruction, and make an acknowledge signal *BACK high to give the bus master
20
notice of the bus master
20
having being relinquished. In response thereto, the bus master
20
accesses the contents of the memory
21
. Upon completion of the access, the bus master
20
relinquishes the external bus
22
by setting the output of the bus master
20
, to which the external bus
22
is connected, to a high impedance state and make the bus request signal *BREQ high to give the microprocessor
10
notice of the bus master
20
having being relinquished.
Even if a memory
23
is connected to the microprocessor
10
via an external bus
24
independent of the external bus
22
, operation of the microprocessor
10
stops accessing while the acknowledge signal *BACK is low. Therefore, the microprocessor
10
can not get access to the memory
23
, and the throughput of a data processing apparatus is lowered. In order to improve the throughput, if bus arbiter regarding the external bus
24
is performed, the control and configuration of the microprocessor
10
becomes complicated.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a processor whose bus ownership arbitrating control is simple even though a plurality of buses are provided, and a data processing apparatus using the same.
In the 1st aspect of the present invention, there is provided a processor comprising: a processor core (
11
) connected to an internal bus (
14
); a first interface circuit (
12
) connected between the internal bus and a first bus (
22
); and a second interface circuit (
13
) connected between the internal bus and a second bus (
23
), wherein the first interface circuit, comprising a first address buffer register (
121
), holds an address on the internal bus in the first address buffer register in response to a read request from the processor core, outputs the content of the first address buffer register onto the first bus when having a bus ownership for the first bus, thereafter provides data on the first bus onto the internal bus, and provides an internal ready signal (*RDYi) through the internal bus to the processor core, wherein the second interface circuit, comprising a second address buffer register (
131
), holds an address on the internal bus in the second address buffer register in response to a read request from the processor core, outputs the content of the second address buffer register onto the second bus, thereafter provides data on the second bus onto the internal bus, and provides an internal ready signal (*RDYj) through the internal bus to the processor core.
With the 1st aspect of the present invention, since the processor core does not need to perform any bus arbitration, the read operation of the processor core through the 1st bus is the same as that through the 2nd bus, and the bus ownership arbitrating operation is needed only between the 1st interface circuit and a bus master connected to the 1st bus, the bus ownership arbitrating control can be simple.
In the 2nd aspect of the present invention, there is provided a processor as defined in the 1st aspect, wherein each of the read request from the processor core to the first or second interface circuit is a combination of an internal address strobe signal (*ASi) and the address.
With the 2nd aspect of the present invention, no special read request signal is required.
In the 3rd aspect of the present invention, there is provided a processor as defined in the 2nd aspect, wherein the first interface circuit comprises a status circuit which stores an idle state when there is no read request signal from the processor core thereto, the first state from receipt of the read request signal until getting a bus ownership for the first bus, and the second state from getting of the bus ownership for the first bus until completing a read operation through the first bus, the first interface circuit performing a bus arbitration depending on the stored state of the status circuit.
With the 3rd aspect of the present invention, since the bus arbitration is carried out depending on the present state, the bus arbitrating control can be simple.
In the 4th aspect of the present invention, there is provided a processor as defined in the 3rd aspect, wherein the first interface circuit (
12
), in the idle state: outputs an acknowledge signal (*BACK) to relinquish a bus ownership of the first bus in response to a bus request signal (*BREQ) from the outside; and holds an address on the internal bus in the first address buffer register in response to the internal address strobe signal (*ASi).
In the 5th aspect of the present invention, there is provided a processor as defined in the 4th aspect, wherein the first interface circuit outputs a bus request signal (*PREQ) in the first state.
In the 6th aspect of the present invention, there is provided a processor as defined in the 5th aspect, wherein the first interface circuit further comprises a data buffer register and in the second state: outputs the content of the first address buffer register on the first bus; outputs an external address strobe signal (*ASo); holds data on the first bus in the data buffer register in response to an external ready signal (*RDYo); outputs the content thereof to the internal bus; and thereafter provides the internal ready signal (*RDYi) to the processor core.
In the 7th aspect of the present invention, there is provided a processor as defined in the 6th aspect, further comprising a between-interface control circuit (
16
) for transmitting the bus request signal (*BREQ) to the first interface circuit in response to the bus request signal from the outside, if the first and second buses are connected in common to each other then in an idle state of the second interface circuit, or else unconditionally.
With the 7th aspect of the present invention, by adding the between-interface control circuit of a simple configuration, it is possible for users of the processors to select whether the 2nd bus is used independent of the 1st bus or the both of them are connected in common, according to respective uses. Thereby, depending upon a use, it is possible to simplify the configuration of a data processing apparatus employing the processor.
In the 8th aspect of the present invention, there is provided a processor as defined in the 7th aspect, further comprising an input terminal of a mode signal for indicating whether or not the first and second buses are connected in common to each other.
With the 8th aspect of the present invention, a common connection detecting circuit is not required.
In the 9th aspect of the present invention, there is provided a processor as defined in the 6th aspect, wherein the first and second buses are connected in common to each other internally, the processor further comprises a between-interface control circuit (
16
A) for, when the second interface circuit is in the idle state, transmitting the bus request signal to the first interface circuit in response to the bus request signal from the outside.
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