Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-29
2004-02-24
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S135000, C711S137000, C711S145000, C710S014000, C712S043000, C712S207000, C712S229000
Reexamination Certificate
active
06697917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a processor that has a prefetch function and that performs processing in a plurality of modes, in which the information to be decoded varies, and has an instruction to dynamically switch the modes.
2. Description of the Related Art
Hitherto there have been proposed many techniques concerning a cache fetch in a processor. Further, a technique of providing a unit, which is adapted to perform processing in a plurality of modes, in a processor has been proposed as a technique concerning such a processor enabled to perform a cache fetch. In the case of the processor having such a unit, when a mode is switched to another mode, the same data string is decoded as a different instruction.
FIG. 1
illustrates a conventional software-implemented mode switching control method for controlling switching of a plurality of modes. That is, when a mode switching instruction is generated (at step S
11
), a trapping process is activated (at step S
12
). Then, if it is verified (at step S
13
) that the mode switching instruction is not illegal, the mode switching instruction is executed (at step S
14
). Thenceforth, instructions are executed in a new mode.
An operation of performing the aforementioned conventional method for switching the plurality of modes is controlled by software. There has been no hardware-implemented mode-switching control method. Thus, such an operation is performed at a low speed. Consequently, the conventional method has a drawback in that an, instruction, which is prefetched before the switching of a mode, may be executed in an erroneous mode.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a processor that has a prefetch function and that performs processing in a plurality of modes, with which information to be decoded varies, and that has an instruction to dynamically switch the modes and that includes means for preventing a malfunction, faster than in the case of being prevented under the control of software, being caused by executing, when a mode is switched, an instruction prefetched before the switching of the mode.
The present invention is accomplished to achieve the foregoing object.
According to an aspect of the present invention, there is provided a processor that has a prefetch function and that performs processing in a plurality of modes, with which information to be decoded varies, and that has an instruction to dynamically switch the modes. In this processor, when a write operation is performed on a register for storing data that contains a bit indicating a current mode, a result of decoding information in a decoding cycle is referred to, regardless of whether or not the value of the bit indicating the current mode is changed, and a cache purge signal is outputted when the result is information represented by a mode switching signal.
Thus, when a mode switching signal is written to the register, a cache purge signal is outputted to a cache memory. Consequently, the valid bit of the cache data is turned off. This prevents data prefetched in one mode from being decoded in a different mode. As a result, operations are normally performed upon completion of switching of the mode.
The processor according to the present invention can obtain similar advantageous effects by referring to a result of issuing an instruction in an issue cycle, instead of referring to the result of decoding information in a decoding cycle.
Further, the processor according to the present invention can provide similar advantageous effects by being adapted so that when a write operation is performed on the register, it is decided whether or not a change in the value of the bit indicating a current mode of the register occurs, and that when a change in the value of this bit is detected, a cache purge signal is outputted to the cache memory.
REFERENCES:
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5860111 (1999-01-01), Martinez, Jr. et al.
patent: 5996071 (1999-11-01), White et al.
patent: 6240508 (2001-05-01), Brown et al.
Ban Daisuke
Matsushima Junya
Nabeya Kenichi
Takeno Takumi
Bragdon Reginald G.
Fujitsu Limited
Vital Pierre M.
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