Processor having a plurality of pipelines and a mechanism for ma

Details Processor having a plurality of pipelines and a mechanism for ma Processor having a plurality of pipelines and a mechanism for ma

1997-04-17

1999-09-21

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1208

Patent

active

059567473

ABSTRACT:
A processor is disclosed. The processor includes a processing unit with a plurality of pipelines. Each of the pipelines execute instructions which may define source register values and destination register values from a register file. A plurality of memories is also provided, each associated with one of the plurality of pipelines respectively. A coherency mechanism is provided to maintain coherency among the register values in the plurality of pipelines and their associated memories. In one embodiment, each memory associated with the plurality of pipelines is a register cache. Each register cache stores register values that were just used or will soon be needed by the instructions that have or will be executed on the pipeline associated with the register cache. A variety of coherency mechanisms may be used to transfer register values from register cache to register cache and maintain coherency among the register values in the plurality of register caches. The coherency protocols include, but are not limited to ownership protocols, snooping protocols and a new protocol that permits only one addressable valid copy of a register value among all the register caches and the register file at a time.

REFERENCES:
patent: 5117493 (1992-05-01), Jensen
patent: 5261053 (1993-11-01), Valencia
patent: 5600848 (1997-02-01), Sproull et al.
patent: 5638526 (1997-06-01), Nakada
Article entitled "Design and Implementation of an Integrated Snooping Data Cache", Gaetano Borriello et al., University of California Berleley, Ca, Computer Science Division, Report No. UCB/CSD/84/199, Sep. 1984.
Johnson, "Superscalar Microprocessor Design", 1991, pp. 10-12, 45-46, 48-50, 107-110, 112-115, 122-125.
Handy, "The Cache Memory Book", 1993, pp. 128-129, 140-158.

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