Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
1998-07-28
2001-03-13
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C710S005000, C710S018000, C713S320000, C713S322000
Reexamination Certificate
active
06202104
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a peripheral control processor or input/output control processor in particular, for automotive, communications, and consumer product applications. Such a peripheral control processor can be generally a direct memory access controller with improved features. Usually, direct memory access controllers (DMA-controller) provide independent functions in a microprocessor controlled system. These DMA-controllers have limited functions and for advanced functions the main microprocessor in the system is needed. Many operations which are based on the transfer of data require simple or advanced modification of the data to be transferred or often the transfer is conditional and maybe stopped or interrupted upon different conditions. If these advanced criteria become too complex interaction between the DMA-controller and the microprocessor of the system is needed. Thus, the overall speed of the system is decreased or the microprocessor is blocked from executing other tasks. Also, the DMA-controller in such systems is only used in special tasks. For a significant period during the operation of the system it is not needed. Nevertheless, in present systems the DMA-control has to be active during these periods and therefore consumes power unnecessarily.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a peripheral control processor with a minimum of power consumption. A further object of the present invention is to provide such a peripheral control processor with a maximum of functionality.
This object is achieved by a processor comprising a central processing unit which is clock driven and has a static design. It further comprises a memory coupled with said central processing unit for storing interrupt routines and data, an interrupt control unit coupled with said central processing unit for generating interrupt signals, an interrupt execution unit for executing interrupt routines. If no interrupt routine is being executed the central processing unit is stopped from operating. It will be practically in a halt-state not executing any instructions.
In a further embodiment the central processing unit in addition comprises a control output, and the processor arrangement further comprises a controllable clock unit generating a processor clock fed to the central processing unit, whereby the controllable clock unit comprises a clock enable input coupled with the interrupt control unit and a clock disable input coupled with the control output of the central processing unit, whereby the clock unit is disabled if no interrupt routine is executed.
A peripheral control processor according to the present invention is an independent processor and is integrated, for example, on a microcontroller chip. The peripheral control processor according to the present invention assists the central processing unit of a microcontroller in many tasks that are normally done by a direct memory access controller in combination with interrupt service routines of a central processing unit.
In another embodiment a processor comprises a central processing unit being clock driven and at least one control output, a memory coupled with the central processing unit for storing interrupt routines and data, an interrupt control unit coupled with the central processing unit for generating interrupt signals, a controllable clock unit generating at least a first and a second processor clock fed to the central processing unit. The first clock is higher than the second clock. The controllable clock unit comprises a clock control input coupled with the interrupt control unit and with the control output of the central processing unit. The clock unit generates the first clock if any interrupt routine is executed and the second clock if no interrupt routine is executed.
The peripheral control processor according to the present invention is completely interrupt driven. No Kernel is provided. Thus, if no interrupt routine is pending, the processor can deactivate itself by disabling the clock signal or it can slow down its clock signal thereby comprising a decreased power consumption. Upon an interrupt the clock signal will re-established and the processor can execute the respective interrupt program. Such a combination of microcontroller and peripheral control processor can be preferably used in battery operated systems because it avoids unnecessary power consumption.
REFERENCES:
patent: 5167024 (1992-11-01), Smith et al.
patent: 5428790 (1995-06-01), Harper et al.
patent: 5442775 (1995-08-01), Whitted, III et al.
patent: 5553236 (1996-09-01), Revilla et al.
patent: 5560020 (1996-09-01), Nakatani et al.
patent: 5592173 (1997-01-01), Lau et al.
patent: 5754883 (1998-05-01), Lim et al.
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5848281 (1998-12-01), Smalley et al.
patent: 5878251 (1999-03-01), Hagiwara et al.
patent: 5894577 (1999-04-01), MacDonald et al.
patent: 6016548 (2000-01-01), Nakamura et al.
patent: 0 458 756 A1 (1991-04-01), None
patent: 0 645 690 A1 (1994-07-01), None
patent: 0 676 686 A3 (1995-03-01), None
patent: 0 676 686 A2 (1995-03-01), None
patent: 08211960 (1996-08-01), None
Cao Chun
Lee Thomas C.
Siemens Aktiengesellschaft
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