Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-05-20
2004-03-30
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C709S209000
Reexamination Certificate
active
06715090
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device such as a processor, and more particularly to a microprocessor which is capable of realizing the high speed operation as well as the low power consumption by controlling substrate biases of a processor circuitry constituted by MOS transistors in accordance with an operation mode of the processor.
At the present time, for realization of a microprocessor, an integrated circuit employing CMOSs is widely used. The power consumption of the CMOS circuit is classified into the dynamic power consumption due to charge and discharge during the switching, and the static power consumption due to a leakage current. Out of them, since the dynamic power consumption is proportional to a power source voltage Vdd squared and hence occupies the large power consumption, in order to promote the low power consumption, it is effective to reduce the power source voltage. Then, in recent years, the power source voltages of many microprocessors have been reduced.
As for the present low power consumption type microprocessor, there is known the microprocessor which includes the power management mechanism and which has a plurality of operation modes provided therein and in accordance therewith, stops the supply of a clock to execution units during the stand-by. By stopping the clock supply, the dynamic power consumption due to the switching in the unnecessary units can be reduced as much as possible. However, the static power consumption due to the leakage current can not be reduced and hence still remains.
Since the operation speed of the CMOS circuit is decreased along with reduction of the power source voltage, in order to prevent the degradation of the operation speed, the threshold voltage of the MOS transistor needs to be reduced in conjunction with the reduction of the power supply voltage. However, since if the threshold voltage is reduced, then the leakage current is remarkably increased, along with the reduction of the power source voltage, the increase of the static power consumption due to the leakage current which was not conventionally large so much becomes remarkable. For this reason, it becomes a problem to realize a microprocessor in which the high speed is compatible with the low power consumption.
As for a method of solving the problem associated with both the operation speed and the leakage current of the MOS transistor circuit, a method wherein the threshold voltage of the MOS transistor is controlled by setting variably the substrate biases is disclosed in JP-A-6-53496.
The description will hereinbelow be given with respect to the device structure for use in setting variably the substrate biases with reference to FIG.
2
.
FIG. 2
shows a cross sectional view of a circuit having the CMOS structure. As shown in the figure, an n type well
205
is formed in a part of a surface layer of a p type well (p type substrate)
201
, an n-channel MOS transistor consisting of an n
+
type source/drain region
202
, a gate oxide film
203
and a gate electrode
204
is formed on a surface of the p type well
201
, and a p-channel MOS transistor consisting of a p
+
type source/drain region
206
, a gate oxide film
207
and a gate electrode
208
is formed on a surface of the n type well
205
.
Normally, the source of the p-channel MOS transistor and the source of the n-channel MOS transistor are respectively connected to the power source voltage (hereinafter, referred as Vdd) and the ground electric potential (hereinafter, referred as Vss), and the drains of the n-channel MOS transistor and the p-channel MOS transistor are connected to the output signal. As for terminals through which the substrate biases are given, Vbp
209
is provided in the n type well
205
of the p-channel MOS transistor, and Vbn
210
is provided in the p type well
201
of the n-channel MOS transistor.
While when employing the device as shown in
FIG. 2
, normally, Vbp
209
is connected to Vdd and Vbn
210
is connected to Vss, during the non-operation of the circuits, these substrate biases are switched so that Vbp
209
is connected to the higher electric potential and Vbn
210
is connected to the lower electric potential, whereby the threshold voltages of the MOS transistors can be increased and hence the leakage current can be reduced.
DISCLOSURE OF THE INVENTION
In order to realize a microprocessor in which the high speed operation is compatible with the low power consumption, it is required that for the processor circuitry, the variable control of the substrate biases as described above is carried out, and during the operation of the processor, the threshold voltages of the MOS transistors are decreased to maintain the high speed operation, while during the stand-by thereof, the threshold voltages are increased to reduce the leakage current. However, in order to control variably the substrate biases of the processor, the timing of reactivating the processor in the proceeding of the operation mode of the processor when switching the substrate biases, in particular in the proceeding of the operation mode from the stand-by state to the operation state is accurately controlled, whereby the malfunction of the processor must be prevented.
The present invention was made in order to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a high speed and low power consumption processor by realizing the above-mentioned substrate bias control, on a processor chip, which is applied to the various operation modes of the processor.
In order to solve the above-mentioned problems, a feature of the present invention is provided by providing: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
In addition, another feature of the processor according to the present invention is that a semiconductor device of the processor chip has a triple well structure, and also the processor main circuit is formed on a well region different from those of the substrate bias switching unit and the operation mode control unit.
In addition, still another feature of the processor according to the present invention is that the operation mode control unit includes, as means for waiting, before restarting the operation of the processor main circuit when switching the biases, until the bias voltages switched thereto are stabilized, either an on-chip timer for measuring a lapse of the time period required for stabilizing the biases, or a sensor for detecting that the biases have been stabilized to predetermined voltages.
In addition, yet another feature of the processor according to the present invention is provided by providing:
the processor main circuit in which the semiconductor device of the processor chip has a triple well structure and is divided into a plurality of functional modules which are respectively formed on the different wells; a substrate bias switching unit for switching the substrate biases to the substrate of the respective functional modules; a operation mode control unit for controlling, in response to execution to make stand-by one functional module or the plurality of functional modules in the processor main circuit, the substrate bias switching unit in such a way that the substrate biases of th
Ishibashi Koichiro
Katsuki Yoichi
Mizuno Hiroyuki
Narita Susumu
Nishii Osamu
An Meng-Al T.
Mattingly Stanger & Malur, P.C.
Nguyen Dustin
Renesas Technology Corporation
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