Processor executing SIMD instructions

Details Processor executing SIMD instructions Processor executing SIMD instructions

2007-02-27

2007-02-27

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

10449788

ABSTRACT:
A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

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Motorola MC68030 user guide 1989, Prentice Hall, 2d Ed pp. 3-32 to 3-33,3-108 to3-109.

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