Processor executing SIMD instructions

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word

Reexamination Certificate

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Details

C712S226000

Reexamination Certificate

active

10668358

ABSTRACT:
A processor according to the present invention includes a decoding unit20, an operation unit40and others. When the decoding unit20decodes Instruction vcchk, the operation unit40and the like judges whether vector condition flags VC0˜VC3(110) of a condition flag register (CFR)32are all zero or not, and (i) sets condition flags C4and C5of the condition flag register (CFR)32to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3are zero, and (ii) sets the condition flags C4and C5to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3are stored in the condition flags C0˜C3.

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