Processor event interface for programmable integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07617471

ABSTRACT:
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of attributes can specify a condition that, when met within at least one memory from the list, causes a signal to be generated to the processor. A description of an event interface for the processor can be automatically created according to the plurality of attributes of the interrupt. The description of the event interface can be incorporated into a description of the circuit design.

REFERENCES:
patent: 2007/0043531 (2007-02-01), Kosche et al.
Seng, Shay Ping, “Method and Apparatus for Interfacing Instruction Processors and Logic in an Electronic Circuit Modeling System”, U.S. Appl. No. 11/633,977, filed Dec. 5, 2006, 23 pp., available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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