Processor employing a power managing mechanism and method of...

Details Processor employing a power managing mechanism and method of... Processor employing a power managing mechanism and method of...

2008-07-08

2008-07-08

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S310000, C713S320000, C713S321000, C713S322000, C713S323000, C713S330000, C713S340000, C712S043000

Reexamination Certificate

active

07398410

ABSTRACT:
A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

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patent: 2005/0283629 (2005-12-01), Tanaka et al.
patent: 2007/0106914 (2007-05-01), Muthukumar et al.

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