Processor, data processing system, and method for...

Details Processor, data processing system, and method for... Processor, data processing system, and method for...

2007-10-30

2007-10-30

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S145000, C711S146000, C711S119000

Reexamination Certificate

active

11130907

ABSTRACT:
In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on a interconnect a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block.

REFERENCES:
patent: 6760819 (2004-07-01), Dhong et al.
patent: 2002/0129211 (2002-09-01), Arimilli et al.
patent: 2005/0154832 (2005-07-01), Steely et al.
patent: 2006/0179241 (2006-08-01), Clark et al.
patent: 2006/0179252 (2006-08-01), Cantin et al.

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