Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-05
2007-06-05
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S123000, C711S125000, C711S133000, C711S136000, C711S142000, C711S143000
Reexamination Certificate
active
10965113
ABSTRACT:
A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
REFERENCES:
patent: 2004/0073756 (2004-04-01), Arimilli et al.
patent: 2005/0132148 (2005-06-01), Arimilli et al.
Guthrie Guy Lynn
Levenstein Sheldon B.
Starke William John
Williams Derek Edward
Bragdon Reginald
Dillon & Yudell LLP
Dinh Ngoc
Gerhardt Diane R.
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