Processor core which provides a linear extension of an addressab

Details Processor core which provides a linear extension of an addressab Processor core which provides a linear extension of an addressab

1996-09-09

1999-06-22

Lane, Jack A.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

711212, G06F 1200

Patent

active

059152664

ABSTRACT:
A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

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Deutsch et al. "Dual-mode Language Programming," IBM Technical Disclosure Bulletin, vol. 11 No. 6 (Nov. 1968).

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