Processor core clock generation circuits

Details Processor core clock generation circuits Processor core clock generation circuits

2006-11-07

2006-11-07

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000, C327S116000

Reexamination Certificate

active

07134036

ABSTRACT:
An invention is provided for generating custom clock frequencies within a processor core. A CPU clock signal propagates through a DLL circuit. Further, a control signal controls the CPU clock signal as the signals propagate through multiple inverters in the DLL circuit. The multiple inverters delay the CPU clock signal and generate multiple output signals. Subsequently, the multiple output signals are combined to generate a higher frequency signal than the CPU clock signal. To control the CPU clock signal, the DLL circuit includes a charge pump to lock in a precise control signal. The charge pump further includes circuitry, such as a Schmitt circuit, to increase and decrease voltage.

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Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu, “A Wide Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE Journal of Solid-State Circuits, vol. 37, No. 8, Aug. 2002, pp. 1021-1027.
Chulwoo Kim, In-Chul Hwang, Sung-Mo (Steve) Kang, “A Low-Power Small-Area ±7.28-ps-Jitter 1-GHz DLL-Based Clock Generator,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1414-1420.

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