Processor-controlled clock-data recovery

Details Processor-controlled clock-data recovery Processor-controlled clock-data recovery

2004-12-23

2010-10-19

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S236000, C375S294000, C375S327000, C375S331000, C375S373000

Reexamination Certificate

active

07817767

ABSTRACT:
A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.

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