Processor capable of preventing sleep/hold state based on a...

Details Processor capable of preventing sleep/hold state based on a... Processor capable of preventing sleep/hold state based on a...

2006-03-14

2006-03-14

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S323000

Reexamination Certificate

active

07013401

ABSTRACT:
The present invention provides a clock control type processor which can permit and accommodate a temporary delay in a processing operation also in a system in which processing times are not constant, and realize the accommodation while reducing the power consumption as much as possible. In this clock control type processor, a block difference detection circuit20detects a difference between a processing block address and a writing block address and outputs a block difference signal105, and a clock control circuit16controls a clock.

REFERENCES:
patent: 5394106 (1995-02-01), Black et al.
patent: 5459846 (1995-10-01), Hyatt
patent: 5920888 (1999-07-01), Shirotori et al.
patent: 6401163 (2002-06-01), Kondo et al.
patent: 6505319 (2003-01-01), Kodama
patent: 6779122 (2004-08-01), George et al.
Xilinx, “HDL Synthesis and Built-In Clock Enables”, Quarterly Journal for Xilinx Programmable Logic Users Xcell 21, second quarter, 1996.

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