Processor bus traffic optimization system for multi-level cache

Details Processor bus traffic optimization system for multi-level cache Processor bus traffic optimization system for multi-level cache

1997-09-16

2000-05-30

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711146, 711141, G06F 1314

Patent

active

060702338

ABSTRACT:
A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations.

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"Extended L2 Directory for L1 Residence Recording", IBM Technical Disclosure Bulletin, vol. 34, No. 8, p. 130-133, Jan. 1992.

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