Processor bus traffic optimization system for multi-level cache

Details Processor bus traffic optimization system for multi-level cache Processor bus traffic optimization system for multi-level cache

1999-01-16

1999-12-07

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711141, G06F 1314

Patent

active

060000155

ABSTRACT:
A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. Utilization is made of a smart-fill algorithm which selects the address locations for placement of new data in a second level cache for a Write operation and after a Read-Miss by analyzing the status values (V,R) for each address in order to minimize the overwriting of valid cache data.

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