Processor array

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07549081

ABSTRACT:
An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.

REFERENCES:
patent: 4601031 (1986-07-01), Walker et al.
patent: 4603404 (1986-07-01), Yamauchi et al.
patent: 4858233 (1989-08-01), Dyson et al.
patent: 5065308 (1991-11-01), Evans
patent: 5253308 (1993-10-01), Johnson
patent: 5795797 (1998-08-01), Chester et al.
patent: 5796937 (1998-08-01), Kizuka
patent: 6408402 (2002-06-01), Norman
patent: 6681341 (2004-01-01), Fredenburg et al.
patent: 2002/0174318 (2002-11-01), Stuttard et al.
patent: 0 180 212 (1986-05-01), None
patent: WO 91/11770 (1991-08-01), None
patent: WO 01/02960 (2001-01-01), None
patent: WO 02/50624 (2002-06-01), None
Popli, S. P., et al., “A Reconfigurable VLSI Array for Reliability and Yield Enhancement,” Proceedings of the International Conference on Systolic Arrays, 1988, pp. 631-642.
John, L. K., et al., “A Dynamically Reconfigurable Interconnect for Array Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, No. 1, Mar. 1998, pp. 150-157.
Shigei, N., et al., “On Efficient Spare Arrangements and an Algorithm with Relocating Spares for Reconfiguring Processor Arrays,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, No. 6, Jun. 1997, pp. 988-995.
Schmidt, U., et al., “Datawave: A Single-Chip Multiprocessor for Video Applications,” IEEE Micro, vol. 11, No. 3, Jun. 1991, pp. 22-25, 88-94.
Chean, M., et al., “A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays,” Computer, IEEE Computer Society, vol. 23, No. 1, Jan. 1990, pp. 55-69.
Kamiura, N., et al., “A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic,” Proceedings of the 23rd International Symposium on Multiple-Valued Logic, 1993, pp. 92-97.
LaForge, L., “Extremally Fault Tolerant Arrays,” Proceedings: International Conference on Wafer Scale Integration, 1989, pp. 365-378.
International Search Report of PCT/GB03/02772, dated Nov. 30, 2004.
Great Britain Search Report of Application No. GB 0216880.5, dated Jan. 28, 2003.
Great Britain Search Report of Application No. GB 0216880.5, dated Oct. 9, 2003.
Great Britain Search Report of Application No. GB 0216880.5, dated Apr. 1, 2005.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Processor array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor array will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4055290

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.