Processor architecture with divisional signal in instruction dec

Details Processor architecture with divisional signal in instruction dec Processor architecture with divisional signal in instruction dec

1996-06-28

1999-06-01

Pan, Daniel H.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395380, 395386, 711209, 711214, G06F 1204, G06F 9345

Patent

active

059095881

ABSTRACT:
An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

REFERENCES:
patent: 4020470 (1977-04-01), Drimak et al.
patent: 4538223 (1985-08-01), Vahlstrom et al.
patent: 5155820 (1992-10-01), Gibson
patent: 5606520 (1997-02-01), Gove et al.
patent: 5636351 (1997-06-01), Lee
patent: 5666510 (1997-09-01), Mitsuishi et al.
patent: 5680598 (1997-10-01), Farrell et al.
patent: 5717946 (1998-02-01), Satou et al.
Lee, Ruby B. "Precision Architecture." IEEE Computer, vol. 22, No. 1, Jan. 1989, pp. 78-89.

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