Processor architecture scheme and instruction set for maximizing

Electrical computers and digital processing systems: memory – Address formation – Operand address generation

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Details

711219, 712220, G06F 934

Patent

active

059875836

ABSTRACT:
A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

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patent: 5832533 (1998-11-01), Agarwal et al.

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