Processor architecture having multi-ported memory

Details Processor architecture having multi-ported memory Processor architecture having multi-ported memory

2006-08-16

2009-10-06

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S001000, C709S213000

Reexamination Certificate

active

07600081

ABSTRACT:
A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N data communication buses. A second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data. N is an integer greater than one.

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