Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-10-09
2003-01-07
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S158000, C710S124000, C710S117000, C370S321000
Reexamination Certificate
active
06505274
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French patent application 97 12634, filed Oct. 9, 1997, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory access control, and more specifically to the control of shared access to a memory by several entities that operate in an asynchronous manner.
2. Description of the Related Art
In conventional devices for application to the field of television, data to be displayed on a television screen is delivered by a screen controller that reads from a random access memory whose contents are the results of logic processing performed by a microprocessor. The clock signals that clock the screen controller and the microprocessor are fully asynchronous (in terms of frequency and phase) and each of these entities may request access to the memory at the same time. A conventional approach to shared access uses “dual-access” memories in which two entities can read from or write to (simultaneously or otherwise) each of the memory locations. Such an approach to shared memory access requires the use of complex memories and can cause problems or errors in certain cases. For example, a problem situation arises when one entity requests a write to a memory location while (almost simultaneously) the other entity wishes to read from the same location.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a time-shared, single-access memory, instead of a physically-shared dual-access memory. In the system, memory access requests are time-shared, and access to memory is managed by a sequencer that segments time into access windows. Each access window is reserved for one of the entities using the memory. Additionally, the sequencer is regulated by an internal clock signal of the highest priority entity. A non-priority (i.e., other or auxiliary) entity must wait for its next access window to read or store data. In this manner, control is accomplished for shared access to a memory by several peripheral entities, which are each clocked by an internal clock signal.
In this system, the priority given to a lower priority entity will cause delays in execution. These delays, within the context of fully asynchronous processes with different periods, are completely unpredictable and non-computable in a deterministic manner. Assuming that such a non-priority process also has real-time constraints, the priority scheme can compromise proper execution. In other words, the response time of the system will vary with respect to the auxiliary process. This is particularly detrimental when the auxiliary entity is a central processing unit that manages an RS-
232
interface (i.e., because the bit rate of the interface may depart from the prescribed specifications due to the random accumulation of delays). Additionally, the response time of the system is variable and probabilistic, and this is injurious for a real-time application.
According to the present invention, in order to prevent the generation of random delays in the execution of data processing by the auxiliary processes, delays are “forced” to a maximum value that preferably corresponds to the potentially worst case. This causes the delay to become fixed, so that the memory behaves like a memory with a “slower” access time but with a completely deterministic response time.
In a first embodiment of the present invention, the memory is a single-access memory, and a priority entity is defined from among the peripheral entities. The other entities, at least one of which includes a central processing unit and an input/output circuit that can store data to be written to the memory (or data extracted from memory to be read by the central processing unit), are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. When a memory access request signal is generated by the central processing unit during a window that is not allocated to the unit, the data in the input/output circuit is enabled during the next time window allocated to the central processing unit. The internal operation of the central processing unit is disabled until a predetermined time that is subsequent to the data enabling time and that is separated from the generation time of the access request signal by a predetermined duration (corresponding to a predetermined number of periods of the internal clock signal of the central processing unit). In one preferred embodiment directed to a television application, a screen controller is the priority entity and data samplers are included among the auxiliary entities. The predetermined duration can be fixed or modifiable by the central processing unit.
The present invention also provides a system for controlling shared access to a random access memory. The system includes a single-access random access memory connected to a data bus and an address bus, and several entities in the form of a priority entity and several auxiliary entities, each of which is clocked by its own internal clock signal. At least one of the auxiliary entities includes a central processing unit. Additionally, each peripheral entity can generate a memory access request signal and includes an input/output circuit connected to the data and address buses. The input/output circuit can store data extracted from or to be written to memory and has a control port for receiving at least one signal for enabling the stored data.
In one preferred embodiment, the system also includes a control interface having a sequencer regulated by the internal clock signal of the priority entity so as to formulate a repetitive time frame that is subdivided into several groups of time windows that are allocated to the peripheral entities. When an access request signal is generated by the central processing unit during a time window not allocated to the unit, a control circuit within the interface acts to deliver the data enabling signal to the input/output circuit of the peripheral entity during a window allocated to the peripheral entity. Further, when the access request signal is generated, an inhibiting circuit within the interface acts to disable the internal operation of the central processing unit until a predetermined time that is subsequent to the receiving of the data enabling signal and that is separated from the time of generation of the access request signal by a predetermined duration (e.g., corresponding to a predetermined number of periods of the internal clock signal of the central processing unit).
According to one embodiment, the inhibiting circuit includes a counter clocked by the internal clock signal of the central processing unit, a comparison circuit that compares the current value of the counter with the predetermined number, and a flip-flop linked to the output of the comparison circuit for delivering a signal for selectively disabling the internal operation of the central processing unit. The inhibiting circuit also includes a detection circuit for detecting transitions of the data enabling signal and an AND gate whose output is linked to the flip-flop and whose two inputs are linked to the outputs of the comparison circuit and the detection circuit. This “disabling” (or inhibiting) of the operation of the central processing unit may involve a complete interruption of the operation of the central processing unit or merely a disabling (or freezing) of the contents of the registers or internal flip-flops so that there is no change in the data delivered by these flip-flops until the disabling signal is deactivated.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples,
Bataille Pierre-Michel
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
Kim Matthew
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