Processor and storage apparatus

Details Processor and storage apparatus Processor and storage apparatus

2005-03-22

2005-03-22

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

C711S154000, C711S168000, C711S169000, C711S200000, C365S230010, C365S230030, C365S230050, C365S230080

Reexamination Certificate

active

06871254

ABSTRACT:
An operating unit operates candidate operation data Da, Db. The candidate operation data Da, Db are contained in two source memories, respectively, or alternatively in one of the two source memories. An address-generating unit generates an address signal Aa and read enable signals RE1a, RE2ain connection with the candidate operation data Da. The address-generating unit further generates an address signal Ab and read enable signals RE1b, RE2bin connection with the candidate operation data Db. Thus, data output from the source memory is controlled with each data to be operated, not with each of the source memory. As a result, data transfer-caused loads can be suppressed. This feature provides a processor having enhanced performance, and further reduces electric power that the processor consumes.

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