Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2000-09-07
2004-08-10
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S034000, C712S215000, C712S245000
Reexamination Certificate
active
06775762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to processors and processor systems, and, more particularly, to a processor that issues instructions to a coprocessor by a predetermined control method and a processor system that comprises such processor and coprocessor.
2. Description of the Related Art
FIG. 1
shows the structure of a conventional processor system. As shown in
FIG. 1
, the conventional processor system comprises a main processor
1
, a memory
3
connected to the main processor
1
, and coprocessors CPR
0
to CPRn connected to the main processor
1
. The main processor
1
comprises an instruction fetch unit
5
connected to the memory
3
, an instruction execution unit
7
connected to the instruction fetch unit
5
, a coprocessor designation register (CR)
11
connected to the instruction execution unit
7
, a coprocessor instruction control unit
13
connected to the instruction fetch unit
5
and the CR
11
, and a register
9
connected to the coprocessor instruction control unit
13
and the instruction execution unit
7
.
FIG. 2
shows the structures of the coprocessor instruction control unit
13
and the instruction execution unit
7
shown in FIG.
1
. The coprocessor instruction control unit
13
comprises an instruction register
100
, a resource decision unit
102
, a resource decoding unit
103
, an exception decoding unit
104
, an exception decision unit
106
, an issuance control unit
109
, a completion control unit
110
, and a scoreboard
111
. The instruction register
100
is connected to the instruction fetch unit
5
, and the resource decoding unit
103
is connected to the instruction register
100
. The resource decision unit
102
is connected to the resource decoding unit
103
, and the exception decoding unit
104
is connected to the instruction register
100
. The exception decision unit
106
is connected to the exception decoding unit
104
, and the issuance control unit
109
is connected to the instruction register
100
, the resource decision unit
102
, and the exception decision unit
106
. The issuance control unit
109
and the completion control unit
110
are connected to the coprocessors CPR
0
to CPRn and the register
9
. The scoreboard
111
is connected to the issuance control unit
109
, the completion control unit
110
, the resource decision unit
102
, and the exception decision unit
106
. The exception decision unit
106
and the issuance control unit
109
are connected to the CR
11
.
The instruction execution unit
7
comprises a decoding unit
115
, a write control unit
129
, and an execution control unit
131
. The decoding unit
115
is connected to the instruction fetch unit
5
, and the write control unit
129
and the execution control unit
131
are connected to the register
9
and the decoding unit
115
. The write control unit
129
is also connected to the CR
11
.
In the processor system having the above structure, the instruction fetch unit
5
fetches an instruction from the memory
3
. If a fetched instruction is to rewrite the coprocessor designation register
11
, the instruction fetch unit
5
supplies the instruction to the instruction execution unit
7
. If a fetched instruction is to a coprocessor instruction, the instruction fetch unit
5
supplies the instruction to the coprocessor instruction control unit
13
. If a fetched instruction is other than the above two types of instruction, the instruction fetch unit
5
supplies the instruction to the instruction execution unit
7
.
The instruction execution unit
7
executes a supplied instruction. If a supplies instruction is to rewrite the coprocessor designation register
11
, the instruction execution unit
7
rewrites the CR
11
by the write control unit
129
.
Meanwhile, the coprocessor instruction control unit
13
controls coprocessor instruction execution in the coprocessors CPR
0
to CPRn by the issuance control unit
109
, the completion control unit
110
, and the scoreboard
111
. The issuance control unit
109
controls the instruction issuance from the main processor
1
to the coprocessors CPR
0
to CPRn. In a case where the resource decision unit
102
determines that a coprocessor instruction supplied from the instruction fetch unit
5
has no data dependency on a preceding coprocessor instruction, and the exception decision unit
106
determines that there is no control dependency due to processing exception, the issuance control unit
109
issues a coprocessor instruction as an issuance signal In (n is an integer of 0 or greater) to a designated coprocessor, and writes the information of the issuance of the issuance signal In in the scoreboard
111
. The “data dependency” refers to a situation in which, depending on the execution result of a preceding coprocessor instruction, a following coprocessor instruction is executed.
The “control dependency due to processing exception” refers to a situation in which an operation cannot continue because of an overflow resulting from an arithmetic operation such as a division using 0 or a floating-point calculation.
In a case where the resource decision unit
102
determines that there is data dependency, the issuance control unit
109
waits until a preceding coprocessor instruction on which a current coprocessor instruction depends, and then issues the current coprocessor instruction as the issuance signal In to a coprocessor designated by the CR
11
. After that, the issuance control unit
109
writes the information of the issuance of the issuance signal In to the scoreboard
111
. The completion control unit
110
of the coprocessor instruction control unit
13
receives a coprocessor instruction execution completion signal Cn (n is an integer of 0 or greater) from the coprocessor that has issued the coprocessor instruction. In response to the coprocessor instruction execution completion signal Cn, the completion control unit
110
then deletes the issuance information of the issuance signal In in the scoreboard
111
.
The coprocessor designation register (CR)
11
designates the number of a coprocessor CPRn (n is an integer of 0 or greater) to be operated. The memory
3
stores instructions including coprocessor instructions to be supplied to the main processor
1
. The register
9
consists of a plurality of storage units.
FIG. 3
shows an example format of coprocessor instructions. An instruction code OP-CODE indicates a process to be executed by one of the coprocessors CPR
0
to CPRn. Operands 1 to n indicate the numbers of the storage units in the register
9
that hold data to be supplied to the coprocessor, or the numbers of the storage units in the register
9
that hold execution results from the coprocessor.
FIG. 4
shows a format of an instruction to rewrite the CR
11
. The operand
1
shown in
FIG. 4
designates one of the storage units in the register
9
that holds a value written in the CR
11
. Any desired information may be stored between the instruction code OP-CODE and the operand
1
in FIG.
4
.
In a case where a supplied coprocessor instruction has no possibility of causing an exceptional process and has no data dependency on a preceding coprocessor instruction, the issuance control unit
109
of the coprocessor instruction control unit
13
issues the supplied coprocessor instruction and writes the issuance information in the scoreboard
111
. In a case where a supplied coprocessor instruction has no possibility of causing an exceptional process but has data dependency on a preceding coprocessor instruction, the issuance control unit
109
waits until the execution of the preceding coprocessor instruction is completed, and then issues the supplied coprocessor instruction. After that, the issuance control unit
109
writes the issuance information in the scoreboard
111
.
In a case where a supplied coprocessor instruction has a possibility of causing an exceptional process but has no data dependency on a preceding coprocessor, the issuance control unit
109
of the coprocessor instruction control uni
Miyake Hideo
Nakamura Yasuki
Suga Atsuhiro
Fujitsu Limited
Pan Daniel H.
Staas & Halsey , LLP
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