Processor and processor method of operation

Details Processor and processor method of operation Processor and processor method of operation

2006-08-01

2006-08-01

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07085887

ABSTRACT:
In one embodiment, the present invention is directed to a processor that comprises an instruction pipeline for executing processor instructions wherein the processor instructions define a memory access size and a cache memory for storing cache lines in a plurality of memory banks that have a block size that is greater than the memory access size, the cache memory including mapping logic for storing contiguous groups of bits, of size equal to the memory access size, in different ones of the plurality of memory banks.

REFERENCES:
patent: 4905188 (1990-02-01), Chuang et al.
patent: 5559986 (1996-09-01), Alpert et al.
patent: 2003/0188105 (2003-10-01), Middleton

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