Processor and method of decompressing instruction bundle

Details Processor and method of decompressing instruction bundle Processor and method of decompressing instruction bundle

2009-05-18

2011-11-01

Faherty, Corey S (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

C712S209000

Reexamination Certificate

active

08051274

ABSTRACT:
The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a program memory and creating an instruction bundle consisting of a sequence of instructions to be processed in parallel. A compression buffer is interposed between the program memory and an instruction decompression unit, such that a compression code read in a previous clock cycle is ready at the beginning of a decompression cycle of the subsequent instruction bundle thereby avoiding a delay due to memory read latency.

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Wolf et al.; A Code Decompression Architecture for VLIW Processors; 2001; IEEE.

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