Processor and method of controlling the same

Details Processor and method of controlling the same Processor and method of controlling the same

2005-05-03

2005-05-03

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

Reexamination Certificate

active

06889315

ABSTRACT:
The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.

REFERENCES:
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patent: 5778219 (1998-07-01), Amerson et al.
patent: 5920710 (1999-07-01), Tan et al.
patent: 6615343 (2003-09-01), Talcott et al.
patent: 0 789 298 (1997-08-01), None
patent: 7-182165 (1995-07-01), None
patent: 2000-222207 (2000-08-01), None
“Rejection of Program Interrupts Generated by Out-of-Order, Speculative Instructions”, IBM Technical Disclosure Bulletin, vol. 37, No. 4A, Apr. 1, 1994, pp. 257-258.

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