Processor and method of arithmetic processing thereof

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S143000, C711S145000, C711S146000, C710S022000

Reexamination Certificate

active

06931495

ABSTRACT:
A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back information in units of address range smaller than that of the cache line, the information indicating that the write-back to the external memory is not yet performed; a mode information storing part which stores specific mode flag information which is set or reset by software in order to determine whether or not to be in a mode for not performing unnecessary write-back operation; and; and a write-back determining part which decides whether or not to write back a certain cache line before performing the DMA transfer based on the non-write-back information, when the specific mode flag is set and the write-back of the cache line is instructed.

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