Processor and method for store gathering through merged store op

Details Processor and method for store gathering through merged store op Processor and method for store gathering through merged store op

1996-10-07

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711220, G06F 1208

Patent

active

058601074

ABSTRACT:
First and second store instructions that target one or more locations in a cache memory are identified. A determination is made whether the cache memory is busy. In response to a determination that the cache memory is busy, the operations specified by the first and second store instructions are merged into a single store operation that subsumes store operations specified by the first and second store instructions. Thereafter, the single store operation is performed.

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