Processor and interrupt controlling method

Details Processor and interrupt controlling method Processor and interrupt controlling method

2007-11-01

2010-12-14

Myers, Paul R (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S264000, C710S267000

Reexamination Certificate

active

07853743

ABSTRACT:
A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the schedule.

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