Processor and instruction set with predict instructions

Details Processor and instruction set with predict instructions Processor and instruction set with predict instructions

1999-07-07

2000-07-18

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing control

Branching

712233, 712234, 712235, 712236, 712237, 712238, 712239, G06F 1500

Patent

active

060921889

ABSTRACT:
A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.

REFERENCES:
patent: 5742804 (1998-04-01), Yeh et al.
patent: 5805878 (1998-09-01), Rahman et al.
patent: 5940857 (1999-08-01), Nakanishi et al.

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