Processor and instruction execution method with reduced...

Details Processor and instruction execution method with reduced... Processor and instruction execution method with reduced...

2005-07-19

2005-07-19

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S218000, C712S200000, C712S206000, C712S215000

Reexamination Certificate

active

06920544

ABSTRACT:
A processor includes a memory unit in which instructions having their constituent bytes stored in ascending address order alternate with instructions having their constituent bytes stored in descending address order. A single address pointer is used to read one instruction by reading up, and another instruction by reading down. The amount of address information needed for program execution is thereby reduced, as one address pointer suffices for two instructions. The address pointer may be provided by a branch instruction that also indicates whether to read up or down. An up-counter and a down-counter may be provided as address counters, enabling the two instructions to be read and executed concurrently. Four address counters may be provided, enabling a branch instruction to designate the execution of from one to four consecutive instructions.

REFERENCES:
patent: 5790564 (1998-08-01), Adams et al.
patent: 5983289 (1999-11-01), Ishikawa et al.
patent: 6538938 (2003-03-01), Fister

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