Processor and data cache with data storage unit and tag...

Details Processor and data cache with data storage unit and tag... Processor and data cache with data storage unit and tag...

2006-08-29

2006-08-29

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S118000, C713S500000, C713S501000, C713S600000

Reexamination Certificate

active

07100012

ABSTRACT:
A processor includes a cache memory with a data storage unit operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first clock frequency. The data storage unit may advantageously be clocked faster than the tag unit and hit/miss logic, such as two times (2×) faster. The processor may also include a replay mechanism for recovering from data speculation when the hit/miss logic or the tag unit signals that speculated data from the higher clocked data storage unit is, in fact, invalid.

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