Processor access control device

Details Processor access control device Processor access control device

2007-02-26

2009-12-08

Phan, Raymond N (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S112000, C710S309000

Reexamination Certificate

active

07631135

ABSTRACT:
A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's individual control bus and a common control bus. A bus selector is disposed between the individual control buses and the common control bus and controlled by a bus arbiter that resolves bus requests on the individual control buses from the processors attempting access to the data memory. The bus arbiter sends a selection command to the bus selector, thereby permitting a specified processor to reach the data memory. A bus monitor counts bus requests and conflicts between them, determines priority of each processor attempting access to the data memory according to the count results, and sends a wait command signal to low-priority processors so as to delay their access to the data memory.

REFERENCES:
patent: 6704821 (2004-03-01), Scandurra et al.
patent: 7149828 (2006-12-01), Hayashi et al.
patent: 7162557 (2007-01-01), Takeda et al.
Patent Abstracts of Japan, Publication No. 06-309276, Published Nov. 4, 1994.
Patent Abstracts of Japan, Publication No. 2001-167076, Published Jun. 22, 2001.

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