Processor

Details Processor Processor

1999-03-30

2001-09-18

Pan, Daniel H. (Department: 2783)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt prioritizing

C710S268000, C710S263000, C710S048000, C711S153000

Reexamination Certificate

active

06292866

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a processor and, more particularly to a processor which is capable of controlling execution of instructions stored in a main storage and capable of performing interruption (interrupt) processing.
BACKGROUND OF THE INVENTION
Currently, most computers adopt Neumann type architecture in which a program is stored in a storage similar to ordinary data, and the program is read from the storage and is executed. Generally, a Neumann type computer is realized as a computer system which includes a computer comprising a processor such as a CPU (Central Processing Unit) for controlling execution of the program and a main storage for temporarily storing the program or the data, I/O (input/output) devices for performing I/O operation, an auxiliary (secondary) storage for storing the program or the data for a long period of time, and the like.
When the program is executed under control of the processor, an instruction such as “operation” or “transfer” contained in the program is read from the main storage, and instruction processing such as operation or transmission of a control signal for directing each part of the computer to perform a transfer process or the like according to the instruction is carried out. The processor includes a program counter for specifying areas in the main storage where instructions to be executed are stored, an instruction register for storing the instructions, and the like. In principle, the processor sequentially reads the instructions and performs instruction processing.
As an example of a technique employed in the processor to realize high-speed processing, there is “pipeline processing”. As described above, basically, the instructions are sequentially read and executed. In the processor, processing is performed in plural stages, including instruction fetch, instruction decoding, instruction execution, outputting operation results, and the like. In the pipeline processing, processing in each stage is carried out in parallel to realize high-speed processing. In sequential processing, until an instruction is subjected to processing in plural stages, processing of a subsequent instruction cannot be started, whereas in the pipeline processing, processing of the subsequent instruction starts without waiting for a completion of the processing of the instructions, which enables high-speed processing. For this reason, most processors recently used adopt pipeline processing.
To be more detailed, in the pipeline processing, an instruction is fetched, and then a subsequent instruction is fetched while performing processing for the fetched instruction in subsequent stages, which processing is called a “prefetch process”. Hence, the processor has a storage area for the instruction under execution and a storage area for the instruction to be prefetched. The instruction to be prefetched is basically determined according to the order of the instructions contained in the program. When the instructions are sequentially prefetched, there is a possibility that the pipeline processing cannot be performed appropriately when “jump” or “branch” is included in the program. In order to perform the prefetch process appropriately, a branch prediction method has been developed.
By the way, various interruptions often occur in the computer system. One important role of the processor is to control processing for these interruptions. The interruption occurs when a request is issued from the peripheral device such as the I/O device or when incorrect processing is performed during execution of the program, and demands that it should be processed with priority even if a specified program is being executed. When the interruption occurs, the processing (program) under execution is interrupted and another processing responding to the interruption is performed. This is called interruption processing.
When a timer or an external device issues an interruption request signal to the processor or when an interruption request is issued during execution of the program, the processor temporarily saves the program under execution and then executes a processing program in response to the interruption request signal. Upon completion of interruption processing, the processor resumes execution of the program from when it was interrupted.
FIG. 7
is a control (execution) flow diagram for explaining control for the interruption processing performed by a general processor according to a prior art. The same figure shows storage state of the main storage which has areas
701
-
703
. The area
701
contains a procedure (program) for interruption processing, the area
702
contains a procedure for performing processing for a specified cause of the interruption, and the area
703
contains a general program such as an application program. The procedure stored in the area
701
includes analyzing the cause of the interruption. The storage area in the main storage are uniquely specified by addresses.
The same figure also shows how the general processor according to the prior art performs control when the interruption occurs while an instruction is contained in the general program is processed. In this case, the processor carries out the procedure for interruption processing in a specified area in the main storage to analyze the cause of the interruption, and then it performs processing for the cause of the interruption.
As shown in
FIG. 7
, when the interruption occurs while the instruction
1
a
stored in an area specified by an address n is executed, in control flow P
701
, the processor executes an instruction
2
a
stored in an area specified by an address AAAA indicating the head of the area
701
. Then, in control flow P
702
a,
the processor executes an instruction
2
b,
and then sequentially executes the following instructions. As a result of this, the processor analyzes the cause of the interruption at the point of an instruction
2
k,
and thereby obtains a starting address of an area which contains the procedure for performing processing for the cause of the interruption. In this case, this procedure is stored in an area starting at an address XXXX. In control flow P
702
b,
the processor executes an instruction
3
a
stored in the area located at the address XXXX, and sequentially executes the following instructions.
FIG. 8
is a timing chart showing the state of the prior art processor which performs such processing. In the figure, there are shown instruction addresses indicating where instructions to be executed are stored and instructions under execution at respective timings.
At timing t
0
, the address n indicating the storage area for the instruction
1
a
is obtained as the instruction address and the instruction
1
a
is executed. When “occurrence of the interruption” is sent to the processor at this point of time, at timing t
1
, the address AAAA indicating the storage area for the instruction
2
a,
i.e., the instruction at the head of the procedure for interruption processing is obtained as the instruction address and the instruction
2
a
is executed. At timing t
2
, the instruction
2
b
subsequent to the instruction
2
a
is executed. The following instructions are sequentially executed and then at timing tk, the cause of the interruption is analyzed, and thereby the address at the head of the procedure for performing processing for the cause of the interruption is obtained. At timing tk+1, the instruction address XXXX is obtained and thereby the instruction
3
a
at the head of the procedure for performing processing for the cause of the interruption is executed.
In some cases, the computer system is extended by increasing peripheral devices or adding application programs. The extension of the system often results in an increased number of causes of the interruption. When the interruption occurs, the prior art general processor carries out the procedure for interruption processing which is stored in a fixed storage area to analyze the cause of the interruption, and then performs processing for the cause of the interruption. Therefo

Affiliated with

Also associated with

Rating

Processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2521168