Processor

Details Processor Processor

2001-03-23

2004-04-13

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S037000

Reexamination Certificate

active

06721905

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor including a self-diagnostic function, and in particular, to a processor, which can carry out a self-diagnosis with respect to an adder-subtracter without requiring an expected value data which evaluates a diagnostic result.
2. Description of the Related Arts
Conventionally, in a manufacture process of an integrated circuit such as a processor including a self-diagnostic function, a TAP (Test Access Port) controller is built in the integrated circuit as a self-diagnostic circuit. Further, in a wafer manufacture step and a package manufacture step, a self-diagnostic test is carried out with respect to a built-in RAM and a built-in arithmetic unit. In this manner, an integrated circuit having a manufacturing defect is found and removed, and thereafter, an integrated circuit passing the self-diagnostic test is used. By doing so, it is possible to prevent a wasteful build-up of LSI package and processor module, and thus, to improve a yield in a process after wafer manufacture.
FIG. 1
is a view showing a basic hardware configuration of a conventional processor. An instruction memory management unit (IMMU)
100
makes an exchange between a logical address and a physical address using an instruction TLB (Translation Look-aside Buffer)
102
, and then, a pre-fetch unit
104
pre-fetches an instruction from an instruction cache
110
to an instruction field
106
via a branch prediction
108
. Further, a secondary cache
112
is interposed between the instruction cache
110
and a processor local inter-connector
114
, and is connected to an external unit via the processor local inter-connector
114
. An instruction fetched from the instruction cache
110
is pre-decoded by a pre-decode unit
116
, and thereafter, is stored in an instruction buffer
118
. Further, a dispatch unit
120
distributes the instruction thus fetched to each of a branch unit
122
, an integer arithmetic unit register file (IEU register file)
124
and a floating-point unit register file (FPU register file)
128
. Following the IEU register file
124
, integer arithmetic units (IE ALU)
130
-
1
and
130
-
2
are provided, and then, execute an integer operation instruction. Thereafter, these integer arithmetic units
130
-
1
and
130
-
2
output the operation result to a completion unit
134
, and then, the operation result is loaded or stored according to an instruction from a load-store unit
126
. Moreover, following the floating-point unit register file
128
, floating-point arithmetic units (FP ALU)
132
-
1
and
132
-
2
are provided, and then, execute a floating-point operation instruction. Thereafter, these floating-point arithmetic units
132
-
1
and
132
-
2
output the operation result to the completion unit
136
, and then, the operation result is loaded or stored according to an instruction from a load-store unit
126
.
FIG. 2
is a view showing a basic configuration of the integer arithmetic unit including an instruction decoder in the processor shown in FIG.
1
. An integer operation instruction from the dispatch unit
138
is latched by a staging latch
144
, and then, is decoded by a decoder
150
. A source register
140
stores a first operand of instruction; on the other hand, a source register
142
stores a second operand of instruction. The first and second operands are latched by staging latches
146
and
148
, respectively, and thereafter, are inputted to an arithmetic unit (ALU)
152
. Then, according to an operation instruction of addition instruction ADD or subtraction instruction SUB decoded by the decoder
150
, the arithmetic unit
152
executes addition or subtraction of two input data so that the operation result is latched by a staging latch
156
. The operation result of the staging latch
156
is stored in a destination register
168
via a staging latch
166
from a multiplexer
164
. Operation instructions other than addition instruction ADD or subtraction instruction SUB decoded by the decoder
150
are latched by the staging latch
154
, and thereafter, are given to a logical instruction unit
162
. At that time, logic operations of AND, OR, NAND, NPR, XOR or XNOR are executed with respect to two data inputted from the staging latches
158
and
160
. The operation result is stored in the destination register
168
via the multiplexer
164
and the staging latch
166
.
The processor including the arithmetic unit as described above is mounted with a self-diagnostic circuit, which is used for an adder-subtracter as shown in
FIGS. 3A and 3B
provided in the arithmetic unit
152
. In a wafer manufacture process and a package manufacture process, the self-diagnostic circuit carries out a self-diagnostic test with respect to a built-in arithmetic unit.
FIG. 24
is a view showing a configuration of a conventional adder-subtracter circuit mounted with a self-diagnostic circuit. For example, a two-input adder-subtracter
202
with carry input Cin is mounted as a test object
200
. An input side of the adder-subtracter
202
is provided with a general register file
204
, selectors
210
and
212
and source registers
214
and
215
. An output of the source register
215
is inputted directly to one of the selector
218
branched into two while being inverted by an inverter
216
so as to be inputted to the other of the selector
218
. The selector
218
makes a changeover of addition input and subtraction input with respect to the adder-subtracter
202
. The operation result of the adder-subtracter
202
is stored in the destination register
220
. The addition and subtraction by the adder-subtracter
202
are carried out on the basis of the addition instruction ADD or subtraction instruction SUB of a decoder
230
decoding an operation code
232
. Now, if each data of the source registers
214
and
216
are set as A and B, in the case where the addition instruction ADD is given from the decoder
230
, the selector
218
selects a value B of the source register
215
. Then, the selector
218
inputs the value to the adder-subtracter
202
while setting the carry input of the adder-subtracter
202
as Cin=0. Therefore, the adder-subtracter
202
executes an addition of C=A+B. Moreover, in the case where the subtraction instruction SUB is given from the decoder
230
, the selector
218
selects an output of the inverter
216
inverting the value B of the source register
215
. Then, the selector
218
inputs the inverted output to the adder-subtracter
202
while setting the carry input of the adder-subtracter
202
as Cin=1. Therefore, the adder-subtracter
202
executes a subtraction of C=A−B. In this case, the subtraction of C=A−B executed by the adder-subtracter
202
is carried out in the following manner. More specifically, an inverted value of B by the inverter
216
is one's complement B
1
's, and then, the carry input Cin=1 is added to the one's complement B
1
's in the adder-subtracter
202
, and thereby, two's complement B
2
's is found. Further, the two's complement B
2
's is added to A, and thereby, the following subtraction C=A−B=A+B
1
's+1=A+B
2
's is carried out. A self-diagnostic controller
228
is provided as a self-diagnostic circuit with respect to the add-subtract circuit as described above. The self-diagnostic controller
228
includes a TAP (Test Access Port) controller
226
and a comparator
234
.
In a processor mounted with the aforesaid self-diagnostic circuit, prior to the start of self-diagnosis, the TAP controller
226
executes the following preparation. More specifically, the TAP controller
226
reads a great many of self-diagnostic input data from the external RAM or the like, and a great many of expected value data obtained when an arithmetic unit is normally operated according to the self-diagnosis using the input data in the general register file
240
. Next, the TAP controller
226
starts t

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