Processing unit in which access to system memory is controlled

Details Processing unit in which access to system memory is controlled Processing unit in which access to system memory is controlled

2000-06-26

2003-09-02

Auve, Glenn A. (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

C712S244000

Reexamination Certificate

active

06615304

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a processing unit equipped with a function of controlling an access (load/store) to a system memory. Particularly, the invention relates to a processing unit capable of improving its processing capacity by reducing the number of synchronization control required at the time of changing over interruption levels (running level).
BACKGROUND OF THE INVENTION
In recent years, along with rapid development of computer technologies, there has been progressed an accelerated increase in the capacity of software to be executed and the capacity of a memory to higher levels. Accordingly, in order to meet this trend of increase in capacities, processing units to be mounted on computers are also required to have higher performance capacities that can execute processing at higher speed.
FIG. 24
is a block diagram that shows a structure of a conventional processing unit.
FIG. 24
shows a structure that one system memory
7
is shared by n processing units
1
1
to
1
n
. Each of the processing units
1
1
to
1
n
makes access to the system memory
7
(or a cache memory
6
1
) according to load/store instructions, thereby to execute loading/storing of data. Further, each of the processing units
1
1
to
1
n
executes various kinds of processing based on processing instructions such as an addition instruction and a subtraction instruction.
In the processing unit
1
1
, an instruction buffer
2
1
buffers the processing instructions and load/store instructions in the sequence of issuance of the instructions. An instruction issuing unit
3
1
issues the processing instruction or the load/store instruction buffered in the instruction buffer
2
1
to a processor
4
1
or to a memory access unit
5
1
. The processor
4
1
executes various kinds of processing according to the processing instruction issued from the instruction issuing unit
3
1
. The processor
4
1
also outputs a busy signal BUSY
1
that shows that the processor
4
1
is currently executing a processing, to the instruction issuing unit
3
1
. After the processor
4
1
has finished the processing, the processor
4
1
stops outputting the busy signal BUSY
1
.
The memory access unit
5
1
stores data into the system memory
7
(or the cache memory
6
1
) or loads data from the system memory
7
(or the cache memory
6
1
), according to the load/store instruction issued from the instruction issuing unit
3
1
. The memory access unit
5
1
also outputs a busy signal BUSY
1
that shows that the memory access unit
5
1
is currently executing a load/store of data, to the instruction issuing unit
3
1
. After the memory access unit
5
1
has finished the load/processing, the memory access unit
5
1
stops outputting the busy signal BUSY
1
.
The processing unit
1
n
has a structure and functions that are the same as the structure and the functions of the processing unit
1
1
. In other words, the processing unit
1
n
consists of an instruction buffer
2
n
, an instruction issuing unit
3
n
, a processor
4
n
, a memory access unit
5
n
, and a cache memory
6
n
.
An interruption level in the processing units
1
1
to
1
n
will be explained next with reference to
FIG. 25A
to FIG.
25
C. When there has been a request for an interruption processing during a period while one of the processing units
1
1
to
1
n
is executing a processing (an arithmetic processing, or a load/store processing), the interruption level is a phase of the processing for executing this interruption processing by suspending the processing of the processing unit. As an example,
FIG. 25A
shows four stages of interruption levels from an interruption level
1
to an interruption level
4
.
According to the example shown in
FIG. 25A
, the interruption level
1
is a level that shows a state that there is no request for an interruption. When an interruption has occurred during the execution of a processing at the interruption level
1
, the interruption level
1
is changed to the interruption level
2
as shown in FIG.
25
B. For example, when an interruption has occurred at time t
1
during the execution of a processing at the interruption level
1
, the interruption level
1
is changed to the interruption level
2
. Thus, the processing at the interruption level
1
shifts to the interruption processing at the interruption level
2
so that the interruption processing at the interruption level
2
is executed at and after the time t
1
. When the interruption processing has been finished at the time t
2
, the interruption level returns to the interruption level
1
from the interruption level
2
. In this way, the interruption processing at the interruption level
2
finishes, and the processing returns to the interruption level
1
.
When there has occurred a further interruption during the execution of an interruption processing at the interruption level
2
, the interruption level
2
shifts to the interruption level
3
as shown in FIG.
25
A. Similarly, when a further interruption has occurred during the execution of an interruption processing at the interruption level
3
, the interruption level
3
shifts to the interruption level
4
. On the other hand, when the interruption processing at the interruption level
4
has been finished, the interruption level returns from the interruption level
4
to the interruption level
3
. When the interruption processing at the interruption level
3
has been finished, the interruption level returns from the interruption level
3
to the interruption level
2
. Similarly, when the interruption processing at the interruption level
2
has been finished, the interruption level returns from the interruption level
2
to the interruption level
1
.
According to the conventional processing unit, in order to improve the processing capacity, there has been introduced a concept called a memory access sequencing model (hereinafter to be referred to as a memory model) that prescribes a relationship between the sequence of issuing load/store instructions and the sequence of actually executing the load/store instructions. For example, there exist two kinds of memory models (
0
,
1
) as shown in FIG.
26
.
In the memory model
0
shown in
FIG. 26
, the sequence of issuing load/store instructions is the same as the execution sequence of the issued load/store instructions. Thus, this is a most severe control model. Therefore, in the memory model
0
, it is not possible to bypass the execution, that is, it is not possible to replace the issued sequence of the load/store instructions at the execution stage. More specifically, in the case of the memory model=0, when the load/store instructions have been issued in the sequence of the load/store instructions A
0
, B
0
, C
0
and D
0
, these load/store instructions A
0
, B
0
, C
0
and D
0
are executed in the same sequence as the issued sequence, as shown in FIG.
27
A.
On the other hand, the memory model
1
shown in
FIG. 26
is a model that has no limit between the sequence of issuing load/store instructions and the sequence of executing the issued load/store instructions. Therefore, in the memory model
1
, it is possible to bypass the execution, that is, it is possible to replace the issued sequence of the load/store instructions at the execution stage. More specifically, in the case of the memory model =1, when the load/store instructions have been issued in the sequence of the load/store instructions A
1
, B
1
, C
1
and D
1
, it is possible to execute these load/store instructions by replacing the sequence of the load/store instruction B
1
with the load/store instruction C
1
, as shown in FIG.
27
B.
The replacement of the execution (bypass execution) is effective when the execution of the later-issued load/store instruction C
1
earlier than the execution of the earlier-issued load/store instruction B
1
can improve the processing speed. In other words, in the case of the memory model
1
, the load/store instructions are executed sequentially in the order of the instructions that can be executed, regardless

Affiliated with

Also associated with

Rating

Processing unit in which access to system memory is controlled does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processing unit in which access to system memory is controlled, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processing unit in which access to system memory is controlled will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3044325