Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-11-21
2006-11-21
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S795000
Reexamination Certificate
active
07139968
ABSTRACT:
A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
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Kabuo Hideyuki
Okamoto Minoru
Stone Kevin Mark
Suzuki Hidetoshi
Yamanaka Ryutaro
Chaudry Mujtaba K.
De'cady Albert
Greenblum & Bernstein P.L.C.
Matsushita Electric - Industrial Co., Ltd.
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