Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-03-19
2003-01-07
Myers, Paul R. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S733000, C712S227000, C711S138000
Reexamination Certificate
active
06505309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microprocessor and a debugging method for a microprocessor and, more particularly, to a debugging technology for a microprocessor incorporating therein a cache memory.
2. Description of the Related Art
In recent years, in order to speed up memory accessing, a cache memory is usually provided in a microprocessor (processing unit). However, with such a microprocessor incorporating therein a cache memory, since no output can be obtained unless a memory access does not find a hit in the cache memory, it is difficult to trace a program to be debugged to thereby understand the program execution state.
Conventionally, in a case where a system using a microprocessor incorporating therein a cache memory is to be debugged, it is a normal practice to use a break function. A break function is a function to make the microprocessor execute a branch at an optional address of a program, and for instance, in Japanese Unexamined Patent Publication (Kokai) No. 7-44419 (JPP'419), a control signal for the cache memory is generated externally of the microprocessor, so that the cache memory is deactivated by this control signal to perform a debugging process.
In other words, this break function is configured so as to make the microprocessor execute a branch at an optional address of a program and prepare a program at a destination for such a branch to thereby confirm whether or not a predetermined processing is being carried out.
As is described above, in JPP'419, an instruction converting circuit is provided for converting an instruction to be read at a specific address by a break demand signal into a branch instruction, so that a breakpoint is set to provide the microprocessor with a memory workspace different from a user workspace. The contents thereof are compared with an address data output from the microprocessor, so as to output a break demand signal when they coincide with each other, to thereby make a background monitor portion function as a memory workspace for a microcomputer development supporting device when a break response signal and the address data are received.
In a technology disclosed in JPP'419, there is a drawback in that, although it can execute real-time debugging, the microprocessor itself cannot-make a judgment on the operation; a cache memory operation (operation in which a cache memory is used) or non-cache memory operation (operation in which a cache memory is not used) and the bus cycle are still unknown when an access is started. In general, a burst access is performed in a cache operation, while no burst access is carried out in a non-cache operation, and the bus cycles (timing at which the bus is used) of the respective operations are different.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a microprocessor (processing unit) in which cache hits in debugging and normal operations are made identical to each other. In addition, another object of the present invention is to have an independent debugger by connecting a ROM emulator to a separate ROM socket, reduce the number of terminals of a ROM socket incorporating therein a debugger, and further dispose a debug routine on the same address.
According to the present invention, there is provided a processing unit, having an operation unit and a cache memory, comprising a debug support unit for outputting a debug mode signal indicating a debug mode when an address of a program being currently executed coincides with an optional address set for debugging; and a non-cache control circuit for controlling the operation of the cache memory via the debug mode signal, whereby the debug mode signal is output externally from the processing unit.
The non-cache control circuit may switch OFF the cache memory so as to make it hold data in the debugging mode, whereby the data so held in the cache memory may be used as they are when the debugging mode is switched to a normal mode. The debug mode signal may be defined at the same timing as that at which an address signal is changed or at a timing prior thereto. When an address signal is decoded externally to the processing unit, the debug mode signal may be involved in the decoding operation when it is asserted, whereby a user area and a debugger area of an external unit may be separated from each other.
The processing unit may further comprise a bus interface unfit having a decoding circuit wherein, when the decoding circuit decodes an address signal inside the processing unit, the decoding circuit may execute decoding, with the debug mode signal being involved when the debug mode signal is asserted, and generates a chip select signal for selection of a width for an external bus.
The processing unit may further comprise a memory management unit having an address converting circuit and a selector, wherein the address converting circuit may convert a logical address from the operation unit for supply to the selector; and the selector may be adapted to select the logical address from the operation unit and the address converted by the address converting circuit with. the debug mode signal for output wherein, when the selector decodes the address signal inside the processing unit, the selector may select the logical address from the operation unit and output the same as it is to thereby dispose a debug routine at the same address. The processing unit may further comprise a main memory that is managed by the memory management unit.
Further, according to the present invention, there is provided a method of debugging a processing unit having an operation unit and a cache-memory, comprising the steps of activating a debug mode and outputting a debug mode signal externally to the processing unit when an address set for debugging and an address of a program being currently executed coincide with each other; and switching OFF the caches memory so as to hold therein data through the activation of the debug mode, whereby the data so held in the cached memory is also used in a normal mode as they are when the debug mode is switched to the normal mode.
The debug mode signal may be defined at the same timing as that at which an address signal is changed or at a timing prior thereto. When the address signal is decoded externally to the processing unit, the debug mode signal may be involved in the decoding when it is asserted, whereby a user area and a debugger area of an external unit may be separated from each other. When the address signal is decoded internally by the processing unit, the de bug mode signal may be involved in the decoding when it is asserted, whereby a chip select signal may be generated for selection of a width for an external bus. When the address signal is decoded internally by the processing unit, the address signal may be separated from those whose addresses are to be converted using the debug mode signal so as for the debug routine to be disposed on the same address.
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Nagano Yasushi
Okabayashi Toru
Fujitsu Limited
Myers Paul R.
Staas & Halsey , LLP
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